The present invention relates to a method and circuit for testing a semiconductor memory such as EEPROM or flash EEPROM, and, more particularly, to a method and circuit for testing a semiconductor memory by writing a checkerboard data pattern.
Conventionally, a semiconductor memory has been tested using test items such as all bits "1," all bits "0" or a checkerboard (1s and 0s are alternately written in adjacent memory cells on a layout). Since a nonvolatile memory takes about 1 msec per one word for writing, writing time occupies a very high ratio in a test time. Thus, some of tests are simplified to shorten the test time. In this case, checkerboard writing is essential for checking interference between bits. Then, for example, to write a checkerboard in a 128 k byte memory, it takes a very long time of 128 k.times.1 msec=128 sec.
In view of the above, there have been proposed semiconductor memories for which the write time can be shortened (Japanese Patent Application Laid-Open Nos. 5-334900 and 9-7380).
FIG. 4 shows a block diagram of a memory cell array disclosed in Japanese Patent Application Laid-open No. 5-334900. The memory cell array constitutes one memory cell with one set of N-channel MOS transistors N11-N12 and one set of memory cell transistors N21-N24. A control gates of the memory cell transistors N21-N24 are connected to a signal line C.sub.G, their sources to a signal line C.sub.L, their drain to sources of the N-channel transistors N11-N14. Drains of the N-channel transistors N11 and N13 are connected to a data select line Y0, drains of the transistors N12 and N14 to a data select line Y1, gates of the transistors N11 and N14 to an address select line X0, gates of the transistors N12 and N13 to an address select line X1.
To write a checkerboard in such memory cell array, all memory cells are first erased (all to "0"), followed by setting even-numbered address select lines X0 to "H," odd-numbered address select lines X1 to "L," and data select lines Y0 and Y1 to "H" to apply a high voltage to the signal line C.sub.G, and to apply the ground voltage to the signal line C.sub.L. This turns on the N-channel transistors N11 and N14 in the memory cell A, thereby electrons being written in floating gates of the memory cell transistors N21 and N24. This would mean that "1" is written in the memory cell A. The memory cell B remains "0."
As such, the memory cell array disclosed in Japanese Patent Application Laid-Open No. 5-334900 can write a checkerboard at a time by crossing the address select lines X0 and X1.
However, this memory cell array has a problem that the memory cell array becomes complicated to attain the above arrangement, causing a larger memory cell array area. FIG. 5 shows a plan view of this memory cell array, FIG. 6 shows a block diagram of a conventional memory cell array in which address select lines are not crossed, and FIG. 7 shows a plan view of the memory cell array of FIG. 6. In FIGS. 5 and 7, S denotes a through hole. As clearly seen from FIG. 5, the memory cell array in which the address select lines are crossed should have a larger number of through holes to connect crossing address select lines, and has a larger area than the memory cell array of FIG. 7 in which the address select lines are not crossed.
Then, FIG. 8 shows a block diagram of a semiconductor memory disclosed in Japanese Patent Application Laid-open No. 9-7380. The semiconductor memory comprises a memory cell array 21 in which a plurality of memory cell transistors are arranged in a matrix, a word line WL connecting to a control gate of a memory cell transistor in each row, a digit line DL connecting to a drain of a memory cell transistors in each column, an X decoder 22 for selecting one word line specified by a row address signal ADr during writing operation, a word line voltage generator circuit 23, a Y decoder 24 and a column select circuit 25 for selecting one digit line specified by a column address signal ADc during the writing operation, and a write circuit 26.
This circuit differs from a conventional one in that further one input is added to a logic gate G23 corresponding to each word line of the X decoder 22 to make an odd-numbered logic gate G23o and an even-numbered logic gate G23e, and that an odd-numbered signal ODr is arranged to be input into an input terminal added with the logic gate G23o, an even-numbered signal EVr to an input terminal added with the logic gate G23e. In addition, further one input is added to a logic gate G43 corresponding to each digit line of the Y decoder 24 to make an odd-numbered logic gate G43o and an even-numbered logic gate G43e. Then, it is arranged that an odd-numbered signal ODc is input into an input terminal added with the logic gate G43o, and an even-numbered signal EVc is added to the input terminal added with the logic gate G43e.
To write a checkerboard in the memory cell array 21, after all memory cells are erased, a write voltage is applied from the word line voltage generator circuit 23 and the write circuit 26 by turning the control signal ACN to "H," the odd-numbered signals ODr and ODc to "L," and the even-numbered signals EVr and EVc to "H." This turns the output of the odd-numbered logic gate G23o to "H" to turn on the odd-numbered N-channel transistor Q22o, thereby the odd-numbered word line WLo becoming 0 V. In addition, the output of the even-numbered logic gate G23e is turned to "L" to turn on the even-numbered P-channel transistor Q21e, thereby the write voltage being applied from the word line voltage generator circuit 23 to the even-numbered word line WLe. On the other hand, the output of the odd-numbered logic gate G43o becomes "H," and the output of the odd-numbered inverter IV42o becomes "L" to turn off the transistor Q5o. The output of the even-numbered logic gate G43e becomes "L," and the output of the even-numbered inverter IV42e becomes "H" to turn on the transistor Q5e, thereby the write voltage being applied from the write circuit 26 to the even-numbered digit line DLe. Thus, "1" is written in all even-numbered memory cell transistors MCee for both the rows and the columns.
Subsequently, a write voltage is applied from the word line voltage generator circuit 23 and the write circuit 26 by turning the control signal ACN to "H," odd-numbered signals ODr and ODc to "H," and the even-numbered signals EVr and EVc to "L." This turns the output of the odd-numbered logic gate G23o to "L" to turn on the odd-numbered P-channel transistor Q21o, thereby the write voltage being applied to the odd-numbered word line WLo. In addition, the output of the odd-numbered logic gate G43o is turned to "L," and the output of the odd-numbered inverter IV42o is turned to "H" to turn on the transistor Q5o, thereby the write voltage being applied from the write circuit 26 to the odd-numbered digit line DLo. Thus, "1" is written in all odd-numbered memory cell transistors MCoo for both the rows and the columns.
Consequently, "1" is written in the memory cell transistors MCee even-numbered in both the rows and the columns and the memory cell transistors MCoo odd-numbered in both the rows and the columns, while "0" is written in the memory cell transistors MCeo even-numbered in the rows and odd-numbered in the columns, and the memory cell transistors MCoe odd-numbered in the rows and even-numbered in the columns.
However, such semiconductor memory has such problem that additional input terminals should be provided for the input terminals for the logic gate G23 of the X decoder 22 and the logic gate G43 of the Y decoder 24 to increase the signal lines ODr, EVr, ODc, and EVc, so that the X and Y decoders become complicated.